In the manufacture and production of semiconductor optoelectronic devices, it is necessary to subject the devices to operation at elevated temperatures for a specified period of time to assure that the fabricated device will satisfactorily operate at elevated temperatures for long periods without failure or unacceptable performance levels. The burn-in process, as the operation at elevated temperatures is called in the art, is performed at the chip-level and the final package level of the device, and is done at constant voltage, constant current or constant power. Normally, lasers and LED's are burned-in at constant current and PIN's are burned-in at constant voltage. Generally, the method used to effect burn-in is dependant on the type of device to be burned-in and the process sequence is selected to minimize the cost of fabrication.
There are several methods that are currently being utilized to effect device burn-in. One of the more primitive techniques is to die and wire bond the device on to a submount or header that has sufficient electrical leads to connect to a burn-in system. This method requires a relatively expensive header or submount to be used in the burn-in process. To this end, the burn-in process done at the discrete element level as in this case results in the discarding of an assembly that is nearly a finished product if the device fails burn-in testing.
A second technique to effect burn-in is to die and wire bond the devices on to a wafer of submounts and bring the required electrical lines to effect burn-in to the devices by a probe card. Done singularly for each device, this method requires a large number of probes to make the needed contacts and can result in both misreadings and actual damage to the device. Accordingly a less cumbersome, more reliable technique is required.
A third method would be to electrically chain the devices together on a wafer in a fashion that would reduce the number of electrical probes required to effect burn-in. In this case, if a single device fails it may interfere with the continued burn-in of the rest of the devices that are connected in the same circuit. This will cause the failure of the burn-in process for all devices in the given test run. Accordingly, a less complex and more reliable technique is required to effect the burn-in process.
What is needed is a less complex and more reliable burn-in procedure for the burn-in of devices mounted on a wafer and not at the discrete element level. This will result in a method that allows the discarding of failed devices at the wafer level by dicing the failed device from the wafer. The cost saving in labor and materials is clearly great as the expensive final packaging is saved for devices that have passed the critical burn-in process.